IC 74160 PDF

By wiring more than one 74LS together cascading , it is possible to make higher count lengths powers of ten. For example, two 74LSs cascaded together would yield a counter capable of decimally counting the range 00 - This counter IC can be cleared set to all zero at any time, by bringing the clear input to logical zero ground. During normal operation, such as counting mode, the clear input must be kept high either directly or through a pull up resistor. This is accomplished by applying the value to be preloaded on the chip's four data input lines, and bringing the load pin to logical zero temporarily. Doing so will disable the counter's operation and the output will latch to reflect the new input upon the next clock pulse.

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We use Cookies to give you best experience on our website. By using our website and services, you expressly agree to the placement of our performance, functionality and advertising cookies. Please see our Privacy Policy for more information. The counter , discharge; follow proper IC Handling Procedures. The counter is reset by a low on the master , ; follow proper IC H andling Procedures.

The counter is reset by a low on the master reset input, MR. NOTES: 1. The counter is reset , devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. The counter is reset , : These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. They are synchronously presettable for application , from the counting logic or the parallel entry lo g ic if either m ode is m om entarily enabled, enters.

Counting and parallel presetting , be loaded into the counter. Two count , I. Handling Procedures. These counters are functionally equivalent to the - T T L counters.

The counter is reset by a low on the master reset ,. Abstract: No abstract text available Text: decade synchronous counter that features an asynchronous reset and look-ahead carry logic. The counter is reset by a low on the master reset input ,. Users should follow p roper I. Two count enables, PE and TE are , are sensitive to electrostatic discharge. U sers should follow proper I. Users should follow proper I. Users should tollow proper I.

Two count enables, PE and TE are , devices are sensitive to electrostatic discharge. Handling Procedures ,. Ordering Information. OK, Thanks We use Cookies to give you best experience on our website. Previous 1 2 Rochester Electronics LLC. Texas Instruments. Truth Table pin diagram and truth table.

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74160 - 74160 Decade Counter with Asynchronous Clear

We use Cookies to give you best experience on our website. By using our website and services, you expressly agree to the placement of our performance, functionality and advertising cookies. Please see our Privacy Policy for more information. Abstract: No abstract text available Text: : These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Abstract: No abstract text available Text: I. Handling Procedures.

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74160 Datasheet PDF

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