STATIC TIMING ANALYSIS INTERVIEW QUESTIONS SAM SONY PDF

Answer W1 : Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path both gate and interconnect and comparing it with constraints clock period to check whether the path meets the constraint. In contrast to the dynamic spice simulation of whole design, static timing analysis performs a worst case analysis using very simple models of device and wire delays. A lookup table model or a simple constant current or voltage source based model of device is used. Elmore delay or equivalent model is used to quickly figure out wire delays. Static Timing Analysis is popular because it is simple to use and only needs commonly available inputs like technology library, netlist, constraints, and parasitics R and C.

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Answer W1 : Static Timing Analysis is a technique of analysing timing paths in a digital logic by adding up delays along a timing path both gate and interconnect and comparing it with constraints clock period to check whether the path meets the constraint.

In contrast to the dynamic spice simulation of whole design, static timing analysis performs a worst case analysis using very simple models of device and wire delays.

A lookup table model or a simple constant current or voltage source based model of device is used. Elmore delay or equivalent model is used to quickly figure out wire delays. Static Timing Analysis is popular because it is simple to use and only needs commonly available inputs like technology library, netlist, constraints, and parasitics R and C.

Static Timing Analysis is comprehensive and provides a very high level of timing coverage. It also honours timing exception to exclude the paths that are either not true path are not exercised in an actual design. A good static timing tool correlates well with actual silicon. Question W2 : What are all the items that are checked by static timing analysis? Answer W2 : Static Timing Analysis is used to check mainly the setup and hold time checks. But it also checks for the assumptions made during timing analysis to be holding true.

Mainly it checks for cells to be within the library characterization range for input slope, output load capacitance. It also checks for integrity of clock signal and clock waveform to guarantee the assumptions made regarding the clock waveforms. Latch Time Borrowing Clock pulse width requirements. Question S1 : Describe a timing path. Answer S1 : For standard cell based designs, following figure illustrates basic timing path. Timing path typically starts at one of the sequential storage element which could be either a flip-flop or a latch.

Active clock edge on this element triggers the data at the output of such element to change. Then data goes through stages of combinational delay and interconnect wires. Each of such stage has its own timing delay that accumulates along the path. Eventually the data arrives at the sampling storage element, which is again a flip-flop or a latch. Also notice for the timing paths in the same clock domain, generating flip-flop clock and sampling flip-flop clocks are derived from a single source, which is called the point of divergence.

In reality, actual start point for a synchronous clock based circuits is the first instance where clocks branch off to generating path and sampling path as shown here in the picture, which is also called point of divergence. To simplify analysis we agree that clock will arrive at very much a fixed time at the clock pin of all sequentials in the design. This simplified the analysis of the timing path. Timing path from one Flipflop to another Flipflop.

Question S2 : What are different types of timing paths? Answer S2 : A digital logic can be broken down into a number of timing paths.

A timing path can be any of the following:. A path between primary input to the d-pin of a register or latch. A path between clock-pin of a register to a primary output. A timing path from primary input to macro input pin. A timing path from macro output pin to primary output pin.

A timing path from a macro output pin to another macro input pin not shown in the figure vii. A path passing through input pin and output pin of a block through combinational logic inside the block. Question S3 : What is a launch edge? Answer S3 : In synchronous design, certain activity or certain amount of computation is done within a clock cycle. Memory elements like flip-flop and latches are used in synchronous designs to hold the input values stable during the clock cycle while the computations are being performed.

Beginning of the clock cycle initiate the activity and by the end of the clock cycle activity has to be completed and results have to be ready. Memory elements in a design transfer data from input to output on either rising or the falling edge of the clock. This edge is called the active edge of the clock. During the clock cycle, data propagates from output of one memory element, through the combinational logic to the input of second memory element.

The data has to meet a certain arrival time requirement at the input of the second memory element. Figure S3. Launch edge and capture edge. This active edge of the clock is called the launch edge, because it launches the data at the output of first memory element, which eventually has to be captured by next memory element along the data propagation path.

Question S4 : What is capture edge? Answer S4 : As we discussed in previous question, the way synchronous circuits work, certain amount of computation has to be done within a clock cycle.

At the launch edge of the clock, memory elements transfer fresh set of data at the output pin of the launching memory elements. This new data, ripples through the combinational logic that carries out the stipulated computation.

By the end of the clock cycle, new computed data has to be available at the next set of memory elements. Because next active clock edge, which signifies the end of one clock cycle, captures the computed results at the D2 pin of the memory element and transfers the results to the Q2 pin for the subsequent clock cycle.

This next active edge of the clock, show in blue at figure 1, is called the capture edge, as it really is capturing the results at the end of the clock cycle. There are some caveats to be aware of.

The data D2 has to arrive certain time before the capture edge of clock, in order to be captured properly. This is called setup time requirement, which we will discuss later. Although it is said that computation has to be done within one clock cycle, it is not always the case.

In general it is true that computation has to be done within one clock cycle, but many times, computation can take more than one cycle. When this happens we call it a multi cycle path.

Question S5 : What is setup time? Answer S5 : For any sequential element e. Actually data needs to be stable for a certain time before clock-capture edge activates, because if data is changing near the clock-capture edge, sequential element latch or flip-flop can get into a metastable state and it could take unpredictable amount of time to resolve the metastability and could settle at at state which is different from the input value, thus can capture unintended value at the output.

The time requirement for input data to be stable before the clock capture edge activates is called the setup time of that sequential element. Question S6 What is hold time? Actually data needs to be held stable for a certain time after clock-capture edge deactivates, because if data is changing near the clock-capture edge, sequential element can get into a metastable state and can capture wrong value at the output. This time requirement that data needs to be held stable for after the clock capture-edge deactivates is called hold time requirement for that sequential.

Question S7 : What does the setup time of a flop depend upon? Answer S7 : Setup time of a flip-flop depends upon the Input data slope, Clock slope and Output load. Question S8 : What does the hold time of a flip-flop depend upon? Question S9 Explain signal timing propagation from one flip-flop to another flip-flop through combinational delay.

Answer S9 Following is a simple structure where output of a flop goes through some stages of combinational logic, represented by pink bubble and is eventually samples by receiving flop. For a flop to correctly capture input data, the input data to flop has to arrive and become stable for some period of time before the capture clock edge at the flop.

This requirement is called the setup time of the flop. Usually you'll run into setup time issues when there is too much logic in between two flop or the combinational delay is too small. Hence this is sometimes called max delay or slow delay timing issue and the constraints is called max delay constraint.

Now you can realize that max delay or slow delay constraint is frequency dependent. If you are failing setup to a flop and if you slow down the clock frequency, your clock cycle time increases, hence you've larger time for your slow signal transitions to propagate through and you'll now meet setup requirements.

Typically your digital circuit is run at certain frequency which sets your max delay. Amount of time the signal falls short to meet the setup time is called setup or max, slack or margin. Figure S9. Signal timing propagation from flip-flop to flip-flop Question S10 Explain setup failure to a flip-flop.

Answer S10 Following figure describes visually a setup failure. As you can see that first flop releases the data at the active edge of clock, which happens to be the rising edge of the clock. The delay from the clock rising to the data changing at output pin is commonly referred to as clock to out delay.

Setup time requirement dictates that input signal be steady during the setup window which is a certain time before the clock capture edge. Also notice that a clock skew is observed at the second flop. The clock to second flop clk2 is not aligned with clk1 anymore and it arrives earlier, which exacerbates the setup failure. This is a real world situation where clock to all receivers will not arrival at same time and designer will have to account for the clock skew.

We'll talk separately about clock skew in details. Figure S Question S11 Explain hold failure to a flip-flop. Answer S11 Like setup, there is a 'Hold' requirement for each sequential element flop or a latch. Therefore it is very crucial that input data be held till hold requirement time is met for the sequential in question. In our figure below, data at input pin 'In' of the first flop is meeting setup and is correctly captured by first flop.

In short in reality there are several reasons for device delay to speed up along the signal propagation path. Question S12 : If hold violation exists in design, is it OK to sign off design? If not, why? Answer S12 : No you can not sign off the design if you have hold violations. Because hold violations are functional failures.

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Static Timing Analysis Interview Questions with Answers

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